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RM0008
Figure 26. Timing diagram
ADC_CLK
SET ADON
Analog-to-digital converter (ADC)
ADC power on
ADC
t STAB
Start 1st conversion
ADC Conversion
Conversion Time
Start next conversion
Next ADC Conversion
(total conv time)
EOC
Software resets EOC bit
11.3.7
Analog watchdog
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a low threshold or above a high threshold. These thresholds are programmed in the
12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be
enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The comparison is done before the alignment (see Section 11.5 ).
The analog watchdog can be enabled on one or more channels by configuring the
ADC_CR1 register as shown in Table 61.
Figure 27. Analog watchdog guarded area
Analog voltage
High threshold
Low threshold
Guarded area
HTR
LTR
Table 61.
Analog watchdog channel selection
Channels to be guarded by analog
ADC_CR1 register control bits (x = don’t care)
watchdog
None
All injected channels
All regular channels
All regular and injected channels
Single (1) injected channel
Single (1) regular channel
AWDSGL bit
x
0
0
0
1
1
AWDEN bit
0
0
1
1
0
1
JAWDEN bit
0
1
0
1
1
0
Single
(1)
regular or injected channel
1
1
1
1. Selected by AWDCH[4:0] bits
Doc ID 13902 Rev 9
203/995
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